The present invention relates to a method for recording and reproducing a video format signal including audio frames having data such as time-axis-compressed audio data and video frames containing video information.
A so-called "SWS" (Still-With-Sound) system is known in which a video format signal including video information and time-axis-compressed audio information or audio data is recorded on a recording medium. Upon playback, the audio data obtained from the recording medium is subjected to time-axis expansion by a memory device or the like so as to be used as an audio accompaniment of still picture reproducing operation.
In the SWS system, the video format signal is obtained by the following process: An analog audio signal is converted into a digital signal by a modulation system having high compression effect such as an adaptive delta modulation (ADM) system. After being compressed, a redundant bit is added, which is an error correcting code, to complete every block of digital data. The digital signal thus processed is written in a time-axis-compressing buffer memory at a sampling frequency f.sub.1. The content of the buffer memory is subsequently read out at a frequency f.sub.2, which is higher than the frequency f.sub.1, so that the audio data is time-axis compressed. The digital data and control data, consisting of a digital start code indicating a digital data insertion start position, a stop code for instructing a still picture reproducing operation, and a data count data indicating the amount of digital data, are inserted in the respective blocks. The video data may be inserted in the remaining blocks.
FIG. 1 shows a conventional device in which, after a data reading unit obtains time-axis-compressed data from the recording medium on which the video format signal formed as described above has been recorded, sound is provided for a still picture provided by the data reading unit.
In FIG. 1, a video format signal outputted by the data reading unit, namely, a video disk player (not shown), is applied through a video output terminal to an image reproducing circuit (not shown) and to a signal separating circuit 1. In the signal separating circuit 1, audio data consisting of digital data including audio information, control data, and a synchronizing signal is separated from the video format signal. The synchronizing signal thus separated is applied to a timing signal generating circuit 2. The audio data outputted by the signal separating circuit 3 is applied to a large capacity buffer memory 3. The control data outputted by the signal separating circuit 3 is applied to digital data start detecting circuit 4, a data count latch circuit 5 and a stop code detecting circuit 6. The digital data detecting circuit 4 operates to generate a pulse when it detects a digital data start code in the control data. The pulse thus generated is applied to the set terminal of a flip-flop 7. The flip-flop 7 operates in such manner that, when a pulse is applied to its set terminal, its Q output is raised to a logic level "1" and, when a pulse is applied to its reset terminal, the Q output is set to a logic level "0". Therefore, when the digital start code is detected, the Q output of the flip-flop 7 is raised to "1", which is applied as a write flag to one input terminal of an AND gate 9. The stop code detecting circuit 6 operates to generate a pulse when it detects a stop code from the control data. The output pulse of the stop code detecting circuit 6 is applied to the set terminal of a flip-flop 8. Accordingly, when the stop code is detected, similar to the case of the flip-flop 7, the Q output of the flip-flop 8 is raised to "1", and this bit is applied as a read flag to one input terminal of an AND gate 10. The data count latch circuit 5 stores the data count data included in the control data.
In writing data into the buffer memory 3 or in reading data out of the buffer memory 3, the output of an address counter 11 is applied to the address input terminal of the buffer memory 3 in order to specify storage positions therein. The address counter 11 is made up of a binary counter which performs a count-up operation in synchronization with the fall of a pulse applied to its clock input terminal and is placed in the initial state when "1" is applied to its clear input terminal. The output of the address counter 11 is further applied to one input port of a coincidence detecting circuit 12, to the other input port of which the output of the data count latch circuit 5 is applied. The coincidence detecting circuit subjects the output of the data count latch circuit 5 and the output of the address counter 11 to comparison and outputs a pulse when the two outputs coincide with each other. The output pulse of the coincidence detecting circuit 12 is applied to the reset terminal of the flip-flops 7 and 8. Accordingly, when the audio data separated by the signal separating circuit 1 has been completely supplied to the buffer memory 3, the Q output of the flip-flop 7 is set to "0", and when the audio data thus supplied has been completely read out of the buffer memory, the Q output of the flip-flop 8 is set to "0".
The timing signal generating circuit 2 applies two pulse signals having different repetition frequencies to the other input terminals of the AND gates 9 and 10, respectively. The timing signal generating circuit 2 is designed so as to produce the two pulses in response to each pulse of the synchronizing signal. When the Q output of the flip-flop 7 is at "1", i.e., when the write flag is on, one of the output pulses of the timing signal generating circuit 2 is applied as a write pulse f.sub.2 (W) to the buffer memory 3 through the AND gate 9. When the Q output of the flip-flop 8 is at "1", i.e., when the read flag is on, the other output pulse of the timing signal generating circuit 2 is applied as a read pulse f.sub.1 (R) to the buffer memory 3 through the AND gate 10. The repetition frequency of the write pulse f.sub.2 (W) is higher than that of the read pulse f.sub.1 (R) so that the audio information, time-axis compressed in the recording operation, is time-axis expanded, i.e., restored.
The write pulse f.sub.2 (W) outputted by the AND gate 9 and the read pulse f.sub.1 (R) outputted by the AND gate 10 are supplied to a NOR gate 13 where the inputted pulses are inverted. The output of the NOR gate 13 is connected to the clock input terminal of the address counter 11. Accordingly, in the case where the write pulse f.sub.2 (W) is supplied to the buffer memory 3 and the latter is placed in the write mode, whenever audio data is written, the address counter 11 counts upwardly so that the specified storage position changes successively. In the case where the read pulse f.sub.1 (R) is applied to the buffer memory 3 and the latter is placed in the read mode, whenever the data is read out, the address counter counts upwardly so that the specified storage position changes successively.
The output pulses of the digital data start detecting circuit 4 and the stop code detecting circuit 6 are applied through an OR gate 14 to the clear input terminal of the address counter 11 to set the address counter 11 to an initial value. Accordingly, when the digital start code is detected, the audio data is written in the buffer memory 3 in storage positions beginning with the storage position which corresponds to the initial value of the counter 11. When the stop code is detected, in the buffer memory 3, the audio data written in the previously designated storage positions is read out beginning with the storage position which corresponds to the initial value of the address counter 11.
The audio data read out of the buffer memory 3 is subjected to error correction in an error correcting circuit and then applied to a deinterleaver 16. The audio data is rearranged into the original data train by the deinterleaver 16 and then applied to a D/A converter 17. The D/A converter 17 is designed so that when the read pulse f.sub.1 (R) is supplied to the clock input terminal thereof, input data is stored and thereafter a voltage corresponding to the input data outputted. The D/A converter 17 outputs an analog audio signal.
The output pulse of the stop code detecting circuit 6 is applied to a player control circuit 18, to which a play signal provided by a play switch (not shown) is also applied. The control circuit 18 controls a video disk player in such a manner that the latter performs a still picture reproducing operation when the stop code detecting circuit outputs a pulse, and it performs an ordinary motion picture reproducing operation when a play instruction signal is produced.
When the video disk player supplies the digital start code and the data count data prior to the audio data recorded over a plurality of frames F.sub.1 as shown in FIG. 2, the flip-flop 7 is set so that the write flag is set and the content of the address counter 11 set to the initial value. At the same time, the data count data is stored in the data count latch circuit 5. The audio data is written in the buffer memory 3 in an amount specified by the data count data. Thereafter, when the stop code is supplied prior to the image information which has been recorded in the image frame F.sub.2, a still picture reproducing operation is carried out. At the same time, the flip-flop 8 is set so that the read flag is turned on, whereupon the audio data written in the buffer memory 3 is read out. As a result, a still picture is reproduced with sound. After all the audio data has been read out of the buffer memory 3 and the reproduction of sound has been accomplished, the following still picture reproduction operation with sound is carried out by performing a suitable operation.
In the above-described video format signal recording and reproducing system, the image frame and the audio data are in the radio of 1 to 1. Therefore, when it is required to provide audio accompaniments in different languages, for instance, Japanese, English and French, for a single still picture, it is necessary to employ a video format signal in which, as shown in FIG. 3, an audio frame is provided for each of three identical still picture frames. In FIG. 3, the term "segment" will be used herein to indicate each of the different sound data groups corresponding to the audio accompaniments in Japanese, English and French.
In the video format signal thus formed, three still picture frames must be provided for the audio accompaniments in three different languages. Moreover, because the audio data for each still picture frame is different in length, the audio frames necessarily have useless parts.